1. Field of the Invention
The present invention relates to an internal voltage generator for a semiconductor device, and more particularly to an apparatus for generating an internal voltage used to drive an internal circuit of the semiconductor device after applying an external voltage. Preferably, the present invention relates to an internal voltage generator for the semiconductor device which generates a stable internal voltage, even if a level of an external voltage is lower than a normal level.
2. Description of the Prior Art
As generally known in the art, an external voltage is applied to a semiconductor device but is not directly used in an internal circuit of the semiconductor device. The first reason is that the internal circuit of the semiconductor device is wrongly operated when directly applying the external voltage to the internal circuit. The second reason is that the potential level is unstable because the external voltage is entered together with a noise.
Due to the above reasons, after the external voltage applied to the semiconductor device passes through an internal buffer, it is generally used as an internal voltage. However, internal voltages used in a semiconductor device have generally various potential levels according to the features of an internal circuit for the semiconductor device.
Such internal voltages do not have significant problems when an external voltage has a normal potential level. However, when the level of the external voltage changes, the internal voltage changes under the influence thereof. In particular, when the internal voltage is unstable, the possibility of an erroneous operation of an internal circuit in the semiconductor device increases. The internal circuit uses the internal voltage as a driving voltage.
Hereinafter, a conventional internal voltage generator for a semiconductor device will be explained with reference to FIGS. 1A, 1B, and 1C.
In general, a semiconductor memory device is divided into a core area and a peripheral area thereof. The core area has a memory cell area. The peripheral area has a driver and an internal voltage generator. The driver drives the core area. Each of the core voltage generators shown in FIGS. 1B and 1C is installed in the peripheral area of a semiconductor memory device, and generates an internal voltage for driving the core area having a memory cell area.
FIG. 1A shows a power up sensing circuit which senses an external voltage applied to a semiconductor memory device. When an external voltage VDD is applied to the semiconductor memory device at the early stage of the operation, an output (pwrup) voltage of the power up sensing circuit is at a low level. When a predetermined time lapses, the output (pwrup) voltage of the power up sensing circuit becomes a high level. Although it is shown in FIG. 2, the output voltage pwrup of the power up sensing circuit having a high level depends upon the level of the external voltage.
FIG. 1B shows a core voltage generator operating before the output voltage pwrup of the power up sensing circuit reaches a high level.
As shown in FIG. 1B, when the output (pwrup) voltage of the power up sensing circuit is at a low level (ground voltage), the level of the core voltage is nearly identical with that of the external voltage VDD.
FIG. 1C shows a core voltage generator operating when the output (pwrup) voltage of the power up sensing circuit becomes a high level. Such a core voltage generator is well-known and details thereof will thus be omitted. When the core voltage generator of FIG. 1C operates, the power up sensing circuit of FIG. 1B does not operate.
In a normal operation of the core voltage generator shown in FIG. 1C, when a reference voltage vro_bandgap is applied to the core voltage generator, an output voltage VCORE has twice the reference voltage. For example, in a semiconductor memory device for receiving an external voltage of 2.5 V, the core voltage is set to about 1.8 V. Accordingly, the reference voltage vro_bandgap applied to the core voltage generator shown in FIG. 1C is about 0.9 V.
FIG. 2A illustrates a direct current voltage waveform of the conventional circuits shown in FIGS. 1A, 1B and 1C.
As shown in FIG. 2A, when an output voltage pwrup of the power up sensing circuit is at a low level (that is, before it changes to a high level), a circuit shown in FIG. 1C operates to output a core voltage VCORE having twice the reference voltage vro_bandgap. When the external voltage VDD exceeds 2.0V, the core voltage generator of FIG. 1C outputs a core voltage VCORE of 1.8 V which is a destination value thereof.
However, in FIG. 2A, after an output voltage pwrup of the power up sensing circuit changes from a low level to a high level, the core voltage VCORE is unstable for a predetermined time. The reason is that the core voltage generator of FIG. 1C does not respond to a change of the output of the power up when it suddenly changes. As apparent from the encircled portion, when the output voltage pwrup of the power up sensing circuit changes from a low level to a high level, degradation of the core voltage occurs. In order to test the semiconductor memory, when an external voltage less than 2.0 V is applied to a semiconductor memory device having an external standard voltage of 2.5 V due to noise, the internal circuit of the semiconductor memory device operates erroneously due to the change of the core voltage VCORE. The internal circuit of the semiconductor device operates by the core voltage VCORE and the core voltage VCORE is an internal voltage.
FIG. 2B illustrates an alternating current voltage waveform of the circuits shown in FIGS. 1A, 1B and 1C. When the external voltage VDD changes, a degration of the core voltage VCORE is great. The core voltage VCORE is used for the internal voltage.